The present invention relates to a semiconductor integrated circuit device comprising highly integrated memories such as DRAM (Dynamic Random Access Memory) devices, more particularly to an effective technique applicable to a fast accessing method for highly integrated memories.
In recent years, high integration of LSI (Large Scaled Integrated Circuit) devices has come to be possible along with the progress of semiconductor manufacturing techniques. This has also made it possible to integrate both large capacity memories and large scaled logic circuits together on one semiconductor chip. In the case of such a semiconductor chip, it is easy to increase the number of data I/O lines thereby to improve the data through-put between memory and logic circuit. This also makes it possible to reduce the power consumption of data I/O operations more and transfer data faster than in a case in which I/O pins provided outside the semiconductor chip are driven. The advantages of such a semiconductor chip are thus expected to be used more and more in the future.
There is a semiconductor chip in which a large capacity memory, a large scaled logic circuit, and a fast operation cache memory are put together. This semiconductor chip is intended to use the cache memory for reducing the difference of the operation speed between the large capacity memory and the large scaled logic circuit. Such a semiconductor chip is described, for example, in xe2x80x9cToru Shimizu, et al., xe2x80x9cA Multimedia 32b RISC Microprocessor with 16 Mb DRAMxe2x80x9d, 1966 IEEE International Solid-State Circuits Conference, Digest of Technical Papers pp.216-217 (hereafter, to be referred to as the prior art technique 1)xe2x80x9d. According to this prior art technique 1, a 32-bit microprocessor, a 2 MB DRAM, and a 2 KB cache memory are connected to each other through a 128-bit wide internal bus. When 128-bit data is transferred, the operation is ended in five cycles between the microprocessor and the DRAM and in one cycle between the microprocessor and the cache memory. Consequently, while the cache memory is hit, the number of data transfer cycles can be reduced to ⅕.
For a memory to be mounted on a semiconductor chip realized, for example, by the prior art technique 1, various functions such as continuous reading function, cache function, access control function, etc. are indispensable. The capacity of the semiconductor chip must also be changed according to how the semiconductor chip is used. However, both large capacity memory and cache memory use many analog circuits in a fast operation required portion respectively. When the function and capacity of a memory are to be changed, therefore, the design of the memory itself must be updated significantly even for a minor change.
Furthermore, in the case of a semiconductor chip realized, for example, by the prior art technique 1, it is very important to make the TAT (Turn Around Time) shorter between decision of the specifications and finish of the product. In order to satisfy this requirement, therefore, the three requirements of enhanced functions, easiness to change the capacity, and a shorter TAT must be achieved together.
Furthermore, when a cache memory is used for fast memory accesses on such a semiconductor chip, a problem arises as follows. While the cache memory is hit, the fast memory access is assured. Once a miss occurs, however, the main memory is accessed, which takes a longer time. This causes the operation of the CPU (Central Processing Unit) to be limited dominantly.
Generally, a DRAM can be accessed fast comparatively if consecutive addresses are accessed in a single page of the DRAM. If another different page is accessed (a page miss occurs), however, the access becomes slow due to the pre-charging of the object, etc., which are indispensable in such a case. There is a method proposed for solving such a problem using a multi-bank structure, thereby hiding such a DRAM page miss. This method is disclosed in the previous application (Japanese Patent Application No.08-301538 (filed on Nov. 13, 1996)) by some inventors of this application.
The method disclosed in the previous application described above, however, cannot avoid such a page miss when in random memory accesses.
Under such the circumstances, it is an object of the present invention to make it easier to design a memory macro provided with various functions and a variable capacity, which is integrated in a large scaled logic circuit such as a microprocessor and an image processor.
It is another object of the present invention to provide a memory that can be interfaced easily with a large scaled logic circuit such as a microprocessor and an image processor.
It is further another object of the present invention to provide a memory that can reduce penalties such as page miss, etc.
Above, other, and further objects, as well as new features of the present invention will be apparent from the description and accompanying drawings in this application.
Hereunder, some representative items of the present invention disclosed in this application will be described briefly.
In order to compose a memory macro (MM) to be mounted in a semiconductor integrated circuit device (chip), a data base (1) is prepared. The data base (1) comprises such function blocks as memory bank modules (10, 11, and 12), a main amplifier module (13), a power supply module (14), a controller module (15), etc. Each function block prepared for the data base (1) is composed so as to allow power supply and signal lines to be connected automatically when the function block is just disposed adjacent to others. This will make it possible to easily design a memory macro provided with various functions and a variable capacity only by changing the types and number of function blocks for composing a large capacity memory and a cache memory respectively.
The controller (BKCONTH) in the memory bank module (11) is provided with an address comparing function (COMP), thereby composing the memory macro (MM3). This will make it possible to compose a memory macro that can be accessed fast without providing any controller outside the memory macro itself when accesses are made to a single page.
The memory macro (MM4) is composed of a plurality of memory bank modules (11) and a controller (17) for controlling the memory bank modules. The controller module (17) is composed so as to manage both address and data by adding an ID (identification) to each of both address and data so as to be correspond each other. This will make it possible to change the address input order and the data output order, thereby outputting earlier-prepared data earlier even when the address is entered after the corresponding data if a page miss occurs, so that the memory access becomes faster.